In the production of integrated circuits, control of the etching process can be crucial to good performance and high production yield. The use of increasingly narrow line widths increases the difficulty of accurately replicating mask patterns into layers underlying the mask. Some of the problems which can result are illustrated in FIGS. 1A-1D for a pair of parallel conductive lines generated over an underlying feature.
In FIG. 1A is shown a cross-section in the x-z plane of a typical wafer at a point in the processing when a mask has been generated but the mask pattern has not yet been replicated into the layer or layers below the mask. The portion of the mask shown in FIG. 1A includes a feature 10 which extends in the y-direction and which is to be replicated into a layer 12. Layer 12 is exposed to etchant gases through the open regions in the mask to etch away the exposed regions of layer 12. This etch step replicates the mask pattern into layer 12 and generates walls of the replicated features extending down into layer 12 from the boundaries 11 of the mask. For some materials and choices of etch parameters, when an anisotropic process (eg. plasma etching in a parallel plate system) is utilized to transfer the mask pattern into layer 12, the resulting feature 13 has curved concave walls as shown in FIG. 1B. The overhang from point 16 to point 17 can produce a number of problems as discussed later. For other materials and process parameters, the resulting feature 14 has nearly vertical walls as shown in FIG. 1C. Some of the problems which can result with either type of wall structure become particularly severe when the height of feature 14 is comparable to or larger than its linewidth.
In FIG. 1D is shown the wafer of FIG. 1C after the mask has been removed and an insulating layer 15 has been deposited on it. As is illustrated in FIG. 1D, the topography of layer 15 reflects the topography of patterned layer 12. Such topography increases the difficulty of accurately patterning layer 15 and any additional layers above layer 15. For example, in a process that utilizes a projection photolithography process to generate masks, the projection photolithography apparatus projects into a focal plane a focussed image of the pattern to be replicated. If the surface of the wafer is not planar, then there is some degradation of the pattern projected onto the wafer surface because of irregular reflections off of non-planar underlying layers. This problem becomes increasingly prevalent as line-widths decrease because, under standard scaling theory, the ratio of the height of a feature to its line-width increases with decrease in line-width so that deviation from surface planarity increases with decrease in line-width.
The sharp corners at points 16 and 18 in FIG. 1D can affect circuit operation because of charge concentration at such corners. The sharp corners at points 16 and 18 in FIG. 1B or at points 19 and 110 in FIG. 1C can also produce in layer 15 a region, indicated by dotted line 114, which etches faster than the remainder of layer 15. The problems which can result from such local high etch rate regions can be seen by considering what happens in the case in which layer 15 is an insulator in which a pair of channels, running in the x-direction and displaced from one another by a distance in the y-direction on the order of a linewidth, are etched clear through layer 15 and then filled with conductive material to form a pair of parallel conductors. During the step of etching the channels, the increased etch rate in the region indicated by dotted line 114 will result in a cavity being generated in that region and this cavity is then filled with conductive material when the channels are filled. Material in such cavities can be difficult to etch away in subsequent etch steps leaving undesired residues. In those cases where the enhanced etch rate is large enough, such cavities can extend clear through the insulating material between the pair of conductive lines, thereby creating unexpected shorting of one line to the other.
Features having the shape of feature 13 in 1B have similar and perhaps more severe problems due to sharp corners 16 and 18 than features having right angled corners like corners 19 and 110 in FIGS. 1C and 1D. Therefore, it is advantageous to utilize a processing technique that generates tapered walls. In one such technique disclosed by S. U. Vim in the reference "Method of Removing Nitride Overhang Ledge By Differential Etch Technique", IBM Technical Disclosure Bulletin, Vol. 21, No. 4, September 1978 beginning on page 1369, a hole having tapered walls is produced by use of both a plasma etch step and a wet etch step. In that process, a silicon body is coated with a silicon dioxide layer on top of which is a silicon nitride layer. A photoresist mask is formed on top of the nitride layer and utilized in an isotropic plasma etch step in which the nitride layer is etched back under the photoresist layer and the portion of the oxide layer exposed through the resulting hole in the nitride layer is also etched part way down to the silicon body. The photoresist mask is removed and then an isotropic wet etch step is applied to complete the etch through the oxide layer and to further etch back the nitride layer. This process does result in tapered walls but only at the expense of a process requiring both wet and dry etch steps.
In another technique disclosed by W. W. Koste, et al in the reference "Via Profiling By Plasma Etching With Varying Ion Energy", IBM Technical Disclosure Bulletin, Vol. 22, No. 7, December 1979, pages 2737-2738, a hard mask which does not etch in a plasma is utilized and the layer to be patterned is first etched part way by an isotropic plasma etch and then the etch is completed by an anisotropic plasma etch. The isotropic etch step produces a wider hole than the anisotropic etch step so that the walls of the resulting hole are tapered. Unfortunately, this process is not compatible with many parallel plate etch systems because it requires the wafer to be raised above the lower electrode. In many systems, the space between electrodes is too small to easily accomodate a pedestal and in any case a custom design would be required.
In a third technique disclosed by J. A. Bondur and H. A. Clark in "Plasma Etching for SiO.sub.2 Profile Control", Solid State Technology, April 1980, p. 122, a photoresist mask is formed on a silicon dioxide layer and then heated so that the resist mask softens and, because of surface tension, develops tapered walls. The etch rate ratio of silicon dioxide to photoresist is controlled to match the ratio between the thicknesses of oxide and photoresist so that, as both are etched in an anisotropic reactive ion etch step, the profile of the resist is replicated into the oxide layer. This technique suffers from the difficulty of ensuring that the etch rate ratio equals the ratio of thicknesses and also limits the profile to the shape assumed by the resist mask during the bake step.